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Hi.
I am wondering why is the 12 mhz clock needed, and is it only needed if you use both spdif in and spdif out to send dejitter data out?
Which is more important in a clock, the 12mhz in the spdif tranceiver or 24.576 in the metronome?
If I want to use an external clock for the spdif tranceiver do I need to remove the 12mhz clock?
Do I connect the external clock to ~ and GND only to make it work?
Does the spdif tranceiver currently provide 3.3v to the 12mhz clock as well?
If I use an external clock does the spdi tranceiver provide 3.3v to it too so the clock needs to be 3.3v or does the external clock have to use its own power supply?
Thank you for your patience.
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This white paper will give you some answers: http://www.wolfsonmicro....IF_receiver_Oct_2006.pdfThe output sample rate is derived from the 12 MHz crystal. So in theory, improving this frequency would improve the jitter performance. The 12 MHz crystal is powered by the chip. If you substitute the crystal with an oscillator, then you need to find the power elsewhere and only use the Xin pin in the chip The external clock connection in the board, I don't know, but check the schematics... According to the schematics, that is clock output... Edited by user Saturday, January 22, 2011 5:39:27 PM(UTC)
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Thanks for the response and the pdf link. According to the pdf link, I'm a little confused. In Figure 1 there is the SPDIF receiver architecture and it seems to talk about two indepedent clocks. I'm assuming the 12mhz crystal clock is connected to the Digital PLL as the "internal immediate clock." Then it talks about another clock that is the "high quality clock source" connected to the PLL. This "high quality clock source" seems to be the 24.576 clock in the Metronome. The Elastic buffer seems to be affected by the 12mhz input clock and the 24.576mhz output clock. So shouldn't the Spdif tranceiver's clock be 24.576mhz as well or is there a reason it is 12mhz? So according to the WM8804 pdf from wolfson, in hardware mode clocking "FREQMODE control is fully automatic to ensure that the MCLK output is maintained at 256fs relatived to the SPDIF received sample rate." "In hardware mode, the OSCCLK must be 12mhz and hence the external crystal (or applied XIN clock) must be 12mhz. No other OSCCLK frequencies are supported in hardware mode." So the MCLK output is the 24.576mhz in the metronome and the OSCCLK is the 12mhz in the spdif tranceiver so that is why it is 12mhz? Edited by user Sunday, January 23, 2011 6:51:22 PM(UTC)
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The high quality clock is the 12 MHz crystal. The other clock is the one embedded in the spdif signal (that is the clock of the source). Metronome comes after the receiver and the clock from the receiver is discarded and a new clock is generated by metronome (and new samples are derived and matched to that new clock). Metronome uses the 25.576 MHz oscillator to generate the new clock. Whether the clock from the receiver or the clock from metronome is better is somewhat open for argument, although in theory the sample rate converter in metro reduces jitter (or remaps it into wide band jitter which shows up as white noise). Then there is the DAC: If you are using OPUS, according to Wolfson, the DAC rather not have an upsampled input because "the DAC works optimally with its internal upsampling".
So in summary, you have the clock from the source embedded in the spdif signal, the clock from the receiver and optionally the clock from metronome.
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I see. Thanks for the clarification. I didn't know the receiver clock wouild be discarded. So if you're using the Metronome after the receiver the only way to install a new external clock would be through the Metronome and it seems from another thread the clock has to use 3.3V, and connect the new external clock signal to SCK and the GND to GND.
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If you are using metronome and want to use an external clock through sck, then that external clock must be synchronized to the signal and metro is used in "pass through" mode. In pass through there is no resampling. If you want to use an external clock that is not synchronized to the signal and have metro generate a new clock that is synchronized to the signal, then the only way is to replace the existing clock in metro. Edited by user Sunday, January 23, 2011 7:38:40 PM(UTC)
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Is the Metronome in "pass through" mode when you put the Disable jumper on to disable the internal clock oscillator? After you install the external clock the only way you can change the sample rate is through 512fs, 256fs, and 128fs, right?
Does anyone know where I can find a 22.5792 or 24.576 mhz 3.3v 1ppm as either an external clock or a replacement clock?
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It is most likely (although the data sheet is not too specific) that bypass mode is the same as removing the device. Whatever shows up in the input, shows up in the output. In other words, you can't ask metro to do anything... If you use an "external" clock, how would you synchronize it to the signal? Edited by user Sunday, January 23, 2011 9:08:57 PM(UTC)
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I don't know. I assumed everything works the same except the internal clock is disabled and somehow the metronome recognizes it and use the external clock instead.
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In bypass mode the signal is buffered.
Lag0a you really need to read and understand the datasheet before you proceed.
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