Atom Feed - Twisted Pear Audio Support - Topic:4 Bit DPLL settings BIIISE Pro - 20Twisted Pear Audio Support - Atom Feedurn:twistedpearaudio-com:AtomFeed:TwistedPearAudioSupport:Topic:4BitDPLLsettingsBIIISEPro-20:1Copyright 2024 Twisted Pear Audio Support2024-03-29T09:56:47Zhttp://www.twistedpearaudio.com/forum/Images/YAFLogo.pngForum Adminhttp://www.twistedpearaudio.comfeedback@twistedpearaudio.comJordohttp://www.twistedpearaudio.com/forum/profile/17730-JordoJordohttp://www.twistedpearaudio.com/forum/profile/17730-JordoYetAnotherForum.NETurn:twistedpearaudio-com:ftPosts:st1:meid26248:14 Bit DPLL settings BIIISE Pro<table class="content postContainer_Alt" width="100%"><tr><td>Hi all,<br /><br />I'm looking for some extra explanation about the 4 Bit DPLL Bandwidth dip switch settings.<br />The BIIISE has a nice description in the integration guide but that concerns a 3 bit setting. <br /><br />I have found the Github description which says:<br /><br />4bit DPLL Bandwidth (switch 5 is the low bit)<br />on = 0 off = 1 - 0b0000=default 0b0001=lowest 0b1111=highest<br /><br />Standard SW2 Dip sw 5-8 are ON = default. <br />I interpreted the following: <br />If switch 5 is the low bit than the setting 5= OFF, 6 = ON, 7 = ON, 8= ON will set the lowest value.<br />Set all to OFF you will set the highest value.<br /><br />But how does it work with all the settings in between? <br />Does someone has a matrix or logic for that?<br /><br />Many thanks!<br /><br />PS: the reason I have to play with this is that I bought an LG TV which I've connected via Toslink --> I2s. <br />Due to some coincidence the LG and ESS make an unfortunate combination. Playing with the DPLL settings would provide the solution: <a target="_blank" rel="nofollow" href="https://www.avforums.com/threads/lg-tvs-optical-audio-output-issue-poll.2368353/" title="https://www.avforums.com/threads/lg-tvs-optical-audio-output-issue-poll.2368353/">see here</a><br /></td></tr></table>2022-01-16T17:14:03-07:002022-01-16T17:14:03-07:00Jordo<table class="content postContainer_Alt" width="100%"><tr><td>Hi all,<br /><br />I'm looking for some extra explanation about the 4 Bit DPLL Bandwidth dip switch settings.<br />The BIIISE has a nice description in the integration guide but that concerns a 3 bit setting. <br /><br />I have found the Github description which says:<br /><br />4bit DPLL Bandwidth (switch 5 is the low bit)<br />on = 0 off = 1 - 0b0000=default 0b0001=lowest 0b1111=highest<br /><br />Standard SW2 Dip sw 5-8 are ON = default. <br />I interpreted the following: <br />If switch 5 is the low bit than the setting 5= OFF, 6 = ON, 7 = ON, 8= ON will set the lowest value.<br />Set all to OFF you will set the highest value.<br /><br />But how does it work with all the settings in between? <br />Does someone has a matrix or logic for that?<br /><br />Many thanks!<br /><br />PS: the reason I have to play with this is that I bought an LG TV which I've connected via Toslink --> I2s. <br />Due to some coincidence the LG and ESS make an unfortunate combination. Playing with the DPLL settings would provide the solution: <a target="_blank" rel="nofollow" href="https://www.avforums.com/threads/lg-tvs-optical-audio-output-issue-poll.2368353/" title="https://www.avforums.com/threads/lg-tvs-optical-audio-output-issue-poll.2368353/">see here</a><br /></td></tr></table>